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🏗️ - Designing / project-template / How we can do the same here, excluding
Between 10/31/2025 23:59 and 12/01/2025 00:00
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Leo Moser (mole99) 11/20/2025 16:00
16:00
You need to set SYNTH_EXCLUDED_CELL_FILE to point to your exclude file.
16:01
You can find the current one in gf180mcu/gf180mcuD/libs.tech/librelane/gf180mcu_fd_sc_mcu7t5v0/synth_exclude.cells
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asic destroyer 11/20/2025 16:03
it is possible to overlay it?
16:03
I don't want to touch the gf180mcu repo
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Leo Moser (mole99) 11/20/2025 16:03
No, unfortunately not. Make a copy of the file in your repository and add the line.
😢 1
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Yes, that's what I did
16:07
But it'd be really nice to understand the actual issue
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asic destroyer 11/20/2025 16:08
But if they are changes in gf180mcu you will not recognize 🙂
16:09
Today you know, but not tomorrow 🙂
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Leo Moser (mole99) 11/20/2025 16:15
Yes, the proper solution is to fix the simulation model of the cell (if that is the issue).
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asic destroyer 11/20/2025 16:20
$ cat 06-yosys-synthesis/chip_top.nl.v | grep gf180mcu_fd_sc_mcu7t5v0__oai21_1 | wc -l 0 lolo (edited)
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Leo Moser (mole99)
Yes, the proper solution is to fix the simulation model of the cell (if that is the issue).
There's a good chance the simulation model is not the issue, since there are many gf180mcu_fd_sc_mcu7t5v0__oai21_2 instances in the design that does pass the GL tests
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urish
There's a good chance the simulation model is not the issue, since there are many gf180mcu_fd_sc_mcu7t5v0__oai21_2 instances in the design that does pass the GL tests
asic destroyer 11/20/2025 22:30
what is the issue then?
22:32
yosys?
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